1. Field of the Invention
The present invention relates to a non-volatile memory device, and more particularly, to a non-volatile memory device to prevent an excessive electron erasing phenomenon without providing additional components, and a method for driving a non-volatile memory device by an erasing bias-condition, a programming-bias condition and a reading bias-condition.
2. Discussion of the Related Art
Recently, as demands for non-volatile memories, for example, flash memories, which can electrically program or erase data increase sharply, geometries of structures of the non-volatile memory undergo many changes.
FIG. 1 is a cross sectional view of a unit memory cell in a non-volatile memory device according to the related art. FIG. 2 is a graph of an erasing threshold voltage and a programming threshold voltage in a non-volatile memory device according to the related art.
As shown in FIG. 1, the unit memory cell of the non-volatile memory device according to the related art includes a tunnel oxide layer pattern 3, a floating gate pattern 4, an ONO (Oxide-Nitride-Oxide) pattern 5, a control gate pattern 6, and source/drain diffusion layers 7/8. At this time, the tunnel oxide layer pattern 3 is formed on an active area of a semiconductor substrate 1, and the floating gate pattern 4 is formed on the tunnel oxide layer pattern 3. Then, the ONO pattern 5 is formed on the floating gate pattern 4, and the control gate pattern 6 is formed on the ONO pattern 5. Also, the source/drain diffusion layers 7/8 are formed in the semiconductor substrate 1 at both sides of the floating gate pattern 4.
The non-volatile memory device according to the related art is comprised of the plurality of memory cells, and a plurality of signal lines for driving the unit memory cells.
In the non-volatile memory device according to the related art, a programming operation and an erasing operation are performed by a logic circuit. That is, in case of the programming operation, electrons leap over an energy barrier of the tunnel oxide layer pattern 3 by a hot carrier injection process, and then the electrons are injected to a potential well of the floating gate pattern 4. In case of the erasing operation, the electrons stored in the potential well of the floating gate pattern 4 are discharged to the semiconductor substrate 11 by F-N tunneling the tunnel oxide layer pattern 3. Accordingly, on performing the programming operation, a threshold voltage of the memory cell increases due to the injection of electrons. Meanwhile, on performing the erasing operation, the threshold voltage of the memory cell decreases.
Thus, since the threshold voltage of the memory cell is varied dependent on the programming operation or the erasing operation, the logic circuit applies a reading voltage to the control gate pattern 6, to determine whether the memory cell is in the program state or the erasing state.
However, the non-volatile memory device according to the related art has the following disadvantages.
First, the non-volatile memory device according to the related art has the complex structure due to the change in size of the active area, the change in thickness of the tunnel oxide layer pattern 3, the change on overlapped area between the source/drain diffusion layers 7/8 and the floating gate pattern 4, the change in size of the floating gate pattern 4, the roughness in surface of the floating gate pattern 4, the change in thickness of the ONO pattern 5, and the damage of the tunnel oxide layer pattern 3. Accordingly, if the erasing operation is performed without the additional process, some of the memory cells may have troubles in that the electrons injected to the floating gate pattern 4 on the programming operation are considerably discharged to the external. That is, as shown in FIG. 2, the threshold voltage of the memory cell is below 0V, thereby causing the trouble of excessively erasing the electrons. Eventually, as shown in the drawing, a wide erasing threshold voltage distribution curve GL1 is formed.
In state that the excessive electron-erasing phenomenon generates, if the additional process is not performed, it is impossible for the logic circuit to read data in another memory cell of a bit line.
Furthermore, the excessive electron-erasing phenomenon has bad effects on the programming operation. In this state, if the additional process for preventing the excessive electron-erasing phenomenon is not performed, a programming threshold voltage distribution curve GL2 also is as wide as the erasing threshold voltage distribution curve GL1. Thus, since a threshold voltage window VW is formed between the programming threshold voltage distribution curve GL2 of the memory cell and the erasing threshold voltage distribution curve GL1 of the memory cell, the threshold voltage window VW decreases largely.
As the threshold voltage window VW formed between the programming threshold voltage distribution curve GL2 and the erasing threshold voltage distribution curve GL1 decreases largely, there are many troubles in setting the plurality of reading voltages for the logic circuit. Accordingly, the memory cell is used for only memory device of storing 1-bit level.
To overcome the excessive electron-erasing phenomenon, it is necessary for the logic circuit to provide an additional complex circuit of re-programming the memory cells from which the electrons are excessively erased. Thus, the non-volatile memory device according to the related art requires the additional complex circuit, thereby lowering the production efficiency of the non-volatile memory device, and increasing the size of non-volatile memory device.